1. Field of the Invention
The present invention relates to frequency synthesizer circuits, and more particularly to frequency synthesizer circuits used for reading or writing data in data storage systems such as, for example, magnetic disk storage systems.
2. Description of Related Art
In data storage systems data is stored on a storage media such as a CD-ROM, writable CD, DVD or other optical disk, magnetic tape, magnetic hard disk, etc. Typically, when data is read from the storage media, some form of data detection circuitry is utilized to process the signal generated from or written to the storage media. In magnetic data storage systems, digital data serves to modulate the current in the read/write head coil so that a series of corresponding magnetic flux transitions may be written on to the medium. To read this recorded data, the read head passes over the medium and transduces the magnetic transitions into electrical pulses that alternate in polarity. These pulses are decoded by circuitry commonly called read/write channel circuitry to reproduce the digital data.
The storage medium generally contains at least two types of information or data. The first type of data may be called user data (sometimes referred to as just "data") and generally includes the data that an end user is saving or retrieving from the medium. The second type of information on the medium, called servo information or servo data, is used to determine the position of the read/write head on the medium. Servo information is generally embedded or written on the medium as part of the medium manufacturing process. Often, the two types of data stored on the medium are stored in alternating zones. For example, when information is to be obtained from the disk type medium it is generally transferred in alternating modes of operation, a "read operation" (for obtaining user data) and a "servo operation" (for obtaining servo information). When information is being transferred to a disk the mode of operation is generally called a "write operation."
Decoding the electrical pulses generated from a disk into a digital sequence is performed in most conventional designs by using a discrete time sequence detector in a sampled amplitude read channel. Discrete time sequence detectors are preferred to analog peak detect read channels since the discrete time systems can compensate for inter-symbol interference (ISI) and non-linearities in the medium, providing more reliable and robust data detection performance. There are several well known discrete time sequence detection methods for use in a sampled amplitude read/write channel circuit including discrete time pulse detection (DPD), partial response (PR) with Viterbi detection (partial response maximum likelihood (PRML) sequence detection), decision-feedback equalization (DFE), enhanced decision-feedback equalization (EDFE), and fixed-delay tree-search with decision-feedback (FDTS/DF). No matter what type of discrete methods are utilized for sampled amplitude read channel systems, an analog to digital converter (ADC) is typically utilized to convert the high frequency data which is contained on disk.
The conversion of the continuous electrical pulse into a discrete sample sequence involves the "sampling" of the input sequence. In data storage systems timing information often needs to be extracted from the data itself. This is usually performed by having a timing loop that can adjust the frequency and phase of sampling to acquire a correctly timed sequence since disk spin speed variations are likely to change the effective frequency and phase of the read data. In an analog timing recovery sequence, a variable frequency oscillator (VFO) is often used since the VFO can be sped up or slowed down depending on the decision of the timing recovery processing circuitry. Typically only the VFO and the sampler (generally an analog to digital converter) need to operate at the required sampling frequency. The VFO is used as part of a phase locked loop (PLL) where the data samples arc used to calculate a frequency and phase error that is fed back to the VFO. The VFO operates around a nominal frequency, which is the channel data rate. The closed loop system will settle (converge) to the correct sampling frequency and phase eventually. Such a system is shown in FIG. 1.
As shown in FIG. 1, a data detection system 5 (for example a read/write channel circuit) is provided. Input data 110 is provided to the data detection system 5 from a storage medium such as, for example, a magnetic hard disk. The data is first provided to a variable gain amplifier (VGA) 12 which in turn provides the data to a low pass filter (LPF) 14. The data from the low pass filter is then provided to an analog to digital converter (ADC) 16 for sampling the data. Offset control 17 may be provided around the analog to digital converter 16 to compensate for conversion offsets. From the analog to digital converter 16 the data is provided to a digital finite impulse response equalization filter (FIR) 18. A gain control circuit 19 may be provided to feedback gain adjustment to the variable gain amplifier 12. After the FIR 18, the data may be further processed by a Viterbi detector 20 and an RLL decoder 22 from which the digital data output 24 may be provid ed. As shown in FIG. 1, the ADC 16 is clocked by a PLL which includes a timing recovery circuit 28 and a VFO 26. The VFO may receive an input to set the nominal center frequency of the VFO. In addition, the VFO might possess a zero phase start (ZPS) circuit that is triggered by the data, which enables it to start the sampling process with a minimal phase error. A frequency synthesizer 35 is also provided to generate the clock for operating the various write circuitry of the data detection system. Further, another synthesizer (not shown) will be utilized to clock the servo data.
Digital timing recovery systems feature a different architecture. The sampling system (the ADC) is driven at a fixed sample frequency, and proper phase and frequency information is obtained by decimating (throwing away invalid samples) and interpolating between valid samples to achieve the correct sampling point. Digital timing recovery schemes are often preferred since they are easier to design, test and reproduce from part to part. The digital timing recovery systems avoid the use of a VFO to sample the data by using a synthesizer to sample the data. The synthesizer is a PLL that can be programmed to run at a set of given frequencies. If a synthesizer were used to sample the data at the nominal channel data rate, the disk spin speed variation s could cause the data to be undersampled. One potential solution to this problem is to oversample the read data by some small percentage that is enough to overcome the disk spin speed variations. In addition, the synthesizer's clock will tend to be asynchronous to the data. A digital PLL may be used to interpolate the sampled data to provide a data sequence that would appear to be correctly sampled to the Viterbi decoder. Such a system is shown in FIG. 1A. The data detection system of FIG. 1A is similar to that of FIG. 1 except for the clocking of the ADC 16 which is accomplished in the circuit of FIG. 1A with a frequency synthesizer 32. Frequency synthesizer 35 is also provided to generate the clock for operating the various write circuitry of the data detection system.
Utilizing the circuit of FIG. 1A, however, requires the read/write channel system to utilize two clocks for any data rate: a write clock which operates at the chosen, or nominal, channel data rate, and a read clock that is slightly higher in frequency from the channel data rate. The read circuitry is generally operated at a higher frequency because of the oversampling. To achieve oversampling, the read clock is usually required to be 2-5% higher in frequency than the data rate. This can be achieved by using 2 frequency synthesizers that are appropriately programmed to the desired frequencies. However, utilizing multiple synthesizers on the same read channel integrated circuit increase circuit size and cost and also creates problems related to cross talk, which causes the frequencies of the two synthesizers to drift towards each other. Cross talk may be significant between the read and write clocks because the frequencies of the two synthesizers are generally close, for example 2-5% apart as mentioned above.